[求助]ise综合问题

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请教各位大侠：下面的综合分析，这条路径明明只有7.166ns的延迟，为什么最小周期却是51.755ns. 另请各位大侠推荐几篇典型的综合报告以及布局布线报告的分析实例， 谢谢了！

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 51.755ns (frequency: 19.322MHz)

Total number of paths / destination ports: 49915 / 2932

-------------------------------------------------------------------------

Delay: 7.166ns (Levels of Logic = 4)

Source: clk_configure/rst_1 (FF)

Destination: base_mult/multsine/BU2/U0/virtex4.pm.v4pm/lut_based.v_parm/adt1[5].lsti.panf/a1g[1].tmp1.add1/a1/no_pipelining.the_addsub/i_q.i_simple.qreg/fd/output_1 (FF)

Source Clock: clk falling 3.6X

Destination Clock: clk rising 3.6X

Data Path: clk_configure/rst_1 to base_mult/multsine/BU2/U0/virtex4.pm.v4pm/lut_based.v_parm/adt1[5].lsti.panf/a1g[1].tmp1.add1/a1/no_pipelining.the_addsub/i_q.i_simple.qreg/fd/output_1

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDE_1:C->Q 4 0.307 0.549 rst_1 (rst_1)

end scope: 'clk_configure'

INV:I->O 305 0.426 2.360 _not00031_INV_0 (_not0003)

begin scope: 'base_mult'

BUF:I->O 304 0.426 2.356 reset_1 (reset_1)

begin scope: 'multsine'

begin scope: 'BU2'

FDE:CE 0.743 U0/virtex4.pm.v4pm/lut_based.v_parm/adt1[5].lsti.panf/a1g[1].tmp1.add1/a1/no_pipelining.the_addsub/i_q.i_simple.qreg/fd/output_1

----------------------------------------

Total 7.166ns (1.902ns logic, 5.264ns route)

(26.5% logic, 73.5% route)